VLSI Chip Design and Simulation with Electric VLSI EDA Tool

This course provides a comprehensive exploration of CMOS VLSI design and simulation, covering IC technology, CMOS structures, historical timelines, processor intricacies, MOS transistor design, non-ideal characteristics, power dissipation, low-power design techniques, and practical insights into CMOS logic gates. Participants will delve into fundamental components and circuit design in the "Analog Circuit CMOS Chip Design and Simulation" module, using the Electric VLSI EDA tool. This includes stick diagrams, tool installation and usage, and hands-on experience in schematic/layout representations, enhancing electronic circuit design proficiency. In the "Digital Circuit CMOS Chip Design and Simulation" module, participants create systematic workflows for schematic/layout designs using the Electric VLSI EDA tool. The curriculum covers logic gates, and half adder circuits, providing a holistic understanding of CMOS logic circuit design. Throughout the course, participants acquire a robust skill set, combining theoretical knowledge with practical expertise in CMOS VLSI design and simulation. By the end of this course, you will be able to:  Develop a profound understanding of Integrated Circuit (IC) technology, exploring its historical timeline and key inventions.  Discuss Moore’s Law and technology scaling, recognizing the importance of processors in Very Large-Scale Integration (VLSI).  Gain proficiency in MOS transistors, explaining their types and comprehending their working process, including operational modes of both PMOS and NMOS transistors.  Describe ideal transistor I-V characteristics and delve into non-ideal transistor characteristics, including leakage currents and their impact on device performance.  Understand the workings of the CMOS inverter, covering both its static behavior and power dissipation characteristics.  Explain components and mechanisms involved in CMOS power dissipation, addressing both static and dynamic aspects.  Explore benefits of low-power design techniques, analyzing factors influencing power consumption, and learning various power reduction techniques.  Understand the purpose of power gating in reducing overall power consumption and learn techniques to minimize short-circuit power consumption.  Explain the fundamentals of CMOS logic gates, including the series and parallel connections of NMOS and PMOS transistors.  Acquire skills in designing basic logic gates using Complementary Metal-Oxide-Semiconductor (CMOS) technology.  Develop skills in designing CMOS circuits using stick diagrams, creating blueprints for physical layouts adhering to semiconductor manufacturing process design rules.  Install and set up Electric VLSI EDA tool for VLSI circuit design, exploring components, schematic and layout editors, and conducting essential checks.  Understand PMOS and NMOS transistor concepts, design schematic and layout representations, perform various checks, and conduct simulations for current-voltage characteristics.  Grasp the CMOS inverter concept, create schematic and layout designs, and simulate the inverter to analyze behavior and characteristics.  Explore common-source and common-drain amplifiers in analog circuit design, designing schematics, layouts, and performing simulations to analyze performance.  Investigate the three-stage oscillator concept, design schematics and layout representations with CMOS inverters, and analyze performance through waveform simulations.  Comprehend CMOS NAND gate concepts, design schematics, validate layouts, and simulate for logical behavior analysis with diverse input scenarios.  Explore various digital circuit elements such as AND, NOR, and OR gates, XOR gate, and half adder, designing schematics, layouts, and performing simulations.

• Introduction to CMOS VLSI
• This module provides a thorough introduction to CMOS structures and functionality, exploring IC technology advantages. It covers the historical timeline of IC technology, Moore's Law, and technology scaling. Participants delve into the crucial role of processors and the intricate process of crafting Integrated Chips from Silica Sand, spanning various stages. The module explores MOS transistor design intricacies, covering types and operational modes. It discusses characteristics of ideal and non-ideal transistors, including diverse leakage types. Factors impacting transistor performance, like temperature sensitivity and environmental variations, are explored. The curriculum covers CMOS transistors design, CMOS inverter design, and analysis of power dissipation, noise margin, and propagation delay in CMOS designs, encompassing power dissipation aspects and mechanisms. The module investigates leakage current sources, low-power design benefits, and factors influencing power consumption. Power reduction techniques, including Dynamic Voltage and Frequency Scaling (DVFS), power gating, and strategies for mitigating short-circuit power consumption, are included. Emphasis is on ultra-low power circuit design, power reduction, and optimization techniques for a holistic understanding of energy-efficient design principles. The module concludes with an overview of CMOS logic gates, addressing PMOS and NMOS transistors design intricacies, series/parallel connections configurations, and practical insights into designing logic gates using CMOS networks.
• Analog Circuit CMOS Chip Design and Simulation Using Electric VLSI EDA Tool
• This module immerses participants in the schematic and layout design of fundamental components and circuits. It commences by introducing the fundamentals of stick diagrams, outlining the rules governing stick diagram and layout design, and providing a practical example for both stick and layout design. Subsequently, the module elucidates the installation process and step-by-step procedures for utilizing the Electric VLSI EDA tool. A comprehensive overview of the tool's built-in functions is provided, along with essential checks and waveform simulation. The module also covers the integration of LTspice with Electric VLSI EDA Tool, enhancing participants proficiency in design exploration. Furthermore, the module offers a concise introduction and procedural guidelines for designing schematic and layout representations of various electronic circuits, including PMOS, NMOS, CMOS inverter, Common Source Amplifier, Common Drain Amplifier, and a three-stage oscillator. Participants gain hands-on experience in representation, simulation, and 3D visualization of layout designs for these circuits. The procedures encompass Design Rule Checking (DRC) and Electrical Rule Checking (ERC), followed by NCC checks to ensure the practical implementation of the designs. This comprehensive approach ensures that participants not only grasp theoretical concepts but also acquire practical skills in the design and verification of electronic circuits using EDA tools.
• Digital Circuit CMOS Chip Design and Simulation Using Electric VLSI EDA Tool
• This module is designed to offer participants a deeper understanding of the schematic and layout design of various CMOS logic circuits. It guides participants through the process of creating a new cell in a predefined library, allowing them to choose between "schematic or layout" as the design approach. Emphasizing a systematic workflow, the module highlights that each design initiates with a schematic cell, subject to Design Rule Checking (DRC) at each step to assess the hierarchy of representations. The design is then simulated, and its characteristics are defined through waveform analysis. Participants will acquire the skills to craft the layout of schematic circuits, incorporating thorough checks such as DRC, Electrical Rule Checking (ERC), and Netlist-to-Component Connectivity (NCC) at the final stage. These checks ensure alignment between the designed layout and schematic, affirming the practical viability of the circuit. The module specifically covers the design of AND gate, OR gate, their complementary gates, XOR gate, and half adder circuits using the Electric VLSI EDA Tool and their characteristic verifications are done through LT spice software.