YoVDO

Zedboard FPGA Tutorial

Offered By: YouTube

Tags

FPGA Courses Linux Courses VHDL Courses Verilog Courses

Course Description

Overview

Explore comprehensive FPGA development using the ZedBoard in this 4.5-hour tutorial series. Unbox and familiarize yourself with the ZedBoard's features, then progress through Linux bootup, LED control, and AXI GPIO interfacing. Master VIVADO and SDK for custom IP creation, including Verilog AXI IP for PWM. Dive into advanced topics like running Tcl scripts, implementing DMA audio demos, and creating custom IPs using VIVADO HLS. Learn Microblaze integration, VHDL programming, and audio processing techniques. Tackle image and video processing projects, including test pattern generation, video DMA implementation, and real-time Sobel edge detection. Gain hands-on experience with the Harrish Corner Detection algorithm, XADC interfacing, and System Generator integration using VIVADO and MATLAB.

Syllabus

Unboxing ZedBoard FPGA & Features Introduction Session by Digitronix Nepal.
Getting Started with ZedBoard with Linux Bootup and Led Blinking by Digitronix Nepal.
Zedboard getting started with VIVADO and SDK Switch Buttons and Led Interfacing with AXI GPIO IP.
Custom IP Upload to Zedboard Revision D in QSPI JTAG Mode via Xilinx VIVADO SDK.
Zedboard Tutorial on Creating Custom Verilog AXI IP of PWM in Vivado by Digitronix Nepal.
Running Tcl Scripts on VIVADO & Zedboard DMA Audio Demo by Digitronix Nepal.
How to create Custom IP on VIVADO HLS targeted for Zedboard FPGA.
Getting Started with Microblaze in VIVADO IPI for Zynq : Zedboard FPGA.
Xilinx VIVADO 2015.4 Creating open example design.
Creating Custom IP on VHDL in VIVADO Design Suit for ZedBoard.
Zedboard Audio Processing Demo by Digitronix Nepal's 8th tutorial on Zedboard.
Test Pattern Generator and Video DMA Implementation for Image/Video Processing with Zynq.
Harrish Corner Detection Algorithm Implementation on VIVADO HLS for Zynq FPGA.
Video Processing with FPGA [Xilinx FPGA]-Online Course Overview.
Learn VHDL Programming with Xilinx VIVADO and Zynq FPGA.
Conditional Statements in VHDL: Learn VHDL Programming with FPGA.
Creating Bootable File for Zynq FPGA.
ZedBoard FMC HDMI with Real Time Sobel Edge Detection.
ZedBoard-XADC & PMOD DA2 interfacing with System Generator [VIVADO+MATLAB].


Taught by

Digitronix Nepal

Related Courses

Introducción al diseño de hardware con Verilog
Galileo University via edX Electrónica Digital Bit a Bit: Diseñando en Verilog para FPGA
Pontificia Universidad Católica de Chile via Coursera Electrónica Digital Bit a Bit: Fundamentos, Verilog y FPGA
Pontificia Universidad Católica de Chile via Coursera FPGA Design for Embedded Systems
University of Colorado Boulder via Coursera Hardware Description Languages for FPGA Design
University of Colorado Boulder via Coursera