The Verilog to Verilog Decompiler

Explore methods for integrated circuit decomposition and hardware decompilation in this conference talk. Delve into techniques for extracting functionality from netlists at a higher abstraction level to reconstruct behavioral Register Transfer Level (RTL) code. Learn about the concept of "hardware decompilation" and its parallels with software decompilation. Discover how existing netlist structure recovery techniques fit into the decompilation pipeline and examine new approaches unique to hardware decompilation. Gain insights into solving computationally hard firmware and hardware security problems, including emerging nondestructive counterfeit detection methods and process automation for hardware security. Compare parsing, recompiling, and control flow concepts between software and hardware domains. Witness a signature matching demo and understand the applications of isomorphism-based matching, topology-based matching, and subgraph mining in hardware decompilation.

Intro
Overview
Introduction
Software For Hardware People
The Verilog 2 Verilog Decompiler
Why Write a Hardware Decompiler?
Why Verilog
Parsing in Software
Hardware for Software People 2
Parsing in Hardware
Primitives and Flipflops
Recompile
Recompiling in Software
Basic Blocks in software
Basic Blocks in Hardware
Graph Representation
Example Graph
Hardware for Software People 3
Functions in Software
Modules in hardware
Signature matching in software
Signature matching in hardware
Isomorphism Based Matching.
Topology Based Matching
Subgraph Mining
Signature Matching Demo
Hardware for software people 4
Software for Software People
Control Flow in software