Stanford Seminar - Mostly Missless Memory in the Mill CPU

This is one of the series of talks about the mill architecture. The particular topic discussed here is Cache Access. Ivan Godard attemps to oversimplify and provide an intuitive understanding for people who are not specialists in the field.

Introduction.
The Mill Architecture.
Wide issue.
Exposed pipeline.
The memory hierarchy.
The load problem.
Every CPU's goal - hide load latency.
Hardware approach - dynamic scheduling.
Several different load problems....
Mill "deferred loads".
Deferred loads vs. alternatives.
Reordering constraints.
So eliminate aliasing.
Alias immunity.
Loads across control flow.
Pickup loads.
Compiler strategy.
The trade-off.
Implementation - the retire station.
Implementation - stream monitoring.
Retire station allocation.
The fine print #1.
The fine print #2.
When stores miss....
Valid bits.
Hierarchy from 40,000 ft..