Multi-Core Computer Architecture - Storage and Interconnects

We are in the era of multi-core systems where even the simplest of handheld devices like a smart phone houses many processors in a single chip. The core counts are ever increasing from 8 to 10 in smart phones to over 100s in super computers. This course will introduce the students to the world of multi-core computer architectures. With the unprecedented growth of data science, on-chip storage systems and inter-core communication framework are getting equal attention as that of processors. This course will focus on delivering an in-depth exposure in memory-subsystems and interconnects of Tiled Chip Multi-Core Processors with few introductory sessions on advanced superscalar processors. The course concludes with pointers to current research standings and on-going research directions for motivating the students to explore further.INTENDED AUDIENCE:Anyone in CSE and related fields (like ECE, EEE, IT etc.) with an interest of exploring Multi-Core Computer ArchitecturePRE-REQUISITE :Final year undergraduates or above in Computer Science and related fields (like ECE, EEE, IT etc.). A basic understanding of Computer Organisation & Architecture will be added advantage.INDUSTRY SUPPORT :Intel, AMD, IBM, HP, Apple, Samsung etc.

Week 1: Fundamentals of instruction pipeline for superscalar processor design
Week 2: Memory hierarchy design, cache memory - fundamentals and basic optimisations
Week 3: Cache memory – advanced optimisations, performance improvement technqiues
Week 4: gem5 simulator – build and run, address translations using TLB and page table
Week 5: DRAM – organisation, access techniques, scheduling algorithms and signal systems.
Week 6: Introduction – Tiled Chip Multicore Processors (TCMP), Network on Chips (NoC)
Week 7: NoC router – architecture, design, routing algorithms and flow control techniques.
Week 8: Advanced topics in NoC and storage – compression, prefetching, QoS.