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QtRVSim - RISC-V Simulator for Computer Architecture Classes

Offered By: DevConf via YouTube

Tags

RISC-V Courses Assembly Language Courses Computer Architecture Courses Pipelining Courses

Course Description

Overview

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Explore a free and open-source RISC-V-based computer system simulator designed for teaching and learning computer systems principles in this 17-minute conference talk from DevConf.cz Mini. Discover how QtRVSim allows students to run assembly programs and observe instruction execution on single-cycle and pipelined microarchitectures. Learn about the simulator's graphical display of major datapath components, including the register file, arithmetic-logic unit, memory caches, peripherals, and control unit with control signals. Gain insights into the current capabilities of the simulator, its potential applications in teaching, the design of its implementation, and opportunities for future development. Access the presentation slides for additional information on this educational tool for computer architecture classes.

Syllabus

QtRVSim – RISC-V Simulator for Computer Architectures Classes - DevConf.cz Mini | November 2022


Taught by

DevConf

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