Stanford Seminar - Instruction Sets Should Be Free- The Case for RISC-V

Explore a Stanford seminar on the RISC-V instruction set architecture, delving into the benefits of freely open ISAs and their potential impact on computing. Learn about the RISC-V background, its base and standard extensions, privileged architecture, and hardware abstraction layer. Discover the four supervisor architectures, Scala embedded language, and the EOS chip roadmap. Compare the RISC-V Rocket core with ARM Cortex A5 and examine the growing list of RISC-V external users. Gain insights into resilient architecture with vector-thread execution and understand the importance of open instruction sets in modern computing.

Introduction.
My first computer.
ASPIRE Acorn Atom Shipped with Schematics.
Benefits from Viable Freely Open ISA.
What Style of ISA?.
RISC-V Background.
ASPIRE RISC-V is NOT an Open-Source Processor.
ASPIRE RISC-V Base Plus Standard Extensions.
"A": Atomic Operations Extension.
Variable-Length Encoding.
ASPIRE "C": Compressed Instruction Extension.
RISC-V Privileged Architecture.
RISC-V Hardware Abstraction Layer.
Four Supervisor Architectures.
Scala Embedded Language.
EOS Chip Roadmap in IBM 45nm SOI (design/fabrication funded by DARPA PERFECT/POEM).
Resilient Architecture with Vector-thread Execution.
ASPIRE "Rocket" Core Alpha Release, Oct 7, 2014.
ARM Cortex A5 vs. RISC-V Rocket.
RISC-V External Users.
ASPIRE Sponsors.