VLSI Design Flow: RTL to GDS

Explore the comprehensive VLSI design flow from RTL to GDS in this nearly two-hour lecture presented by Prof. Sneh Saurabh from IIIT Delhi. Gain valuable insights into the intricate process of transforming Register-Transfer Level (RTL) designs into the final Graphic Design System (GDS) format used for chip fabrication. Delve into key stages of the VLSI design process, including synthesis, floor planning, placement, routing, and verification. Learn about industry-standard tools and methodologies employed in modern integrated circuit design, and understand the challenges and considerations at each step of the design flow. Whether you're a student, engineer, or professional in the semiconductor industry, this in-depth lecture offers a thorough overview of the VLSI design process, equipping you with essential knowledge for successful chip design and implementation.

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