YoVDO

Logical Effort and Parasitic Delay in NAND and NOR Gates - Lecture 4.7

Offered By: NPTEL-NOC IITM via YouTube

Tags

Digital Circuit Design Courses Circuit Analysis Courses

Course Description

Overview

Save Big on Coursera Plus. 7,000+ courses at $160 off. Limited Time Only!
Explore the concepts of logical effort and parasitic delay in NAND and NOR gates through this 33-minute lecture. Derive the expressions for these crucial parameters, gaining a deeper understanding of their impact on digital circuit design and performance optimization.

Syllabus

4.7 - Logical effort and Parasitic delay


Taught by

NPTEL-NOC IITM

Related Courses

VLSI Physical Design
Indian Institute of Technology, Kharagpur via Swayam Hardware Modeling Using Verilog
Indian Institute of Technology, Kharagpur via Swayam การออกแบบวงจรดิจิทัล | Digital Circuit Design
Mahidol University via ThaiMOOC Verilog HDL Through Examples
Udemy System Design Through Verilog
Indian Institute of Technology Guwahati via Swayam