YoVDO

Extracting Capacitances of 3-NAND Gate for Delay Estimation - Lecture 4.4

Offered By: NPTEL-NOC IITM via YouTube

Tags

Digital Circuit Design Courses Logic Gates Courses Inverters Courses Propagation Delay Courses

Course Description

Overview

Save Big on Coursera Plus. 7,000+ courses at $160 off. Limited Time Only!
Learn how to extract capacitances for estimating propagation delay in a 3-NAND gate through this informative lecture. Explore the process of calculating both falling and rising delays, and discover techniques for sizing transistors to match the rising and falling resistances of a 2:1 (unit) inverter. Gain valuable insights into delay estimation and transistor sizing for optimal circuit performance.

Syllabus

4.4 - Extracting capacitances of 3-Nand gate for delay estimation


Taught by

NPTEL-NOC IITM

Related Courses

Solar Energy: Photovoltaic (PV) Systems
Delft University of Technology via edX
Multilevel Converters for Medium/High-Power Applications
Georgia Institute of Technology via edX
Power Electronics
Indian Institute of Technology Delhi via Swayam
Devices to Circuits
NPTEL via YouTube
Advanced Power Electronics and Control
NPTEL via YouTube