Switching Circuits and Logic Design

This course will discuss the basic background of switching circuits, and discuss techniques for mapping the theory to actual hardware circuits. Synthesis and minimization techniques of combinational and sequential circuits shall be discussed in detail. Designing circuits using high-level functional blocks shall also be discussed. The course will closely follow the undergraduate curriculum existing in most engineering colleges.INTENDED AUDIENCE: Any Engineering Students/FacultyPREREQUISITES: Basic knowledge of electronics and electrical circuitslINDUSTRY SUPPORT: TCS, Wipro, CTS, Google, Microsoft, HP, Intel, IBM

Week 1 : Introduction to number systems and codes, error detection and correction, binary arithmetic.
Week 2 : Switching primitives and logic gates, logic families: TTL, CMOS, memristors, all-optical realizations.
Week 3 : Boolean algebra: Boolean operations and functions, algebraic manipulation, minterms and maxterms, sum-of-productsand product-of-sum representations, functional completeness.
Week 4 : Minimization of Boolean functions: K-map method, prime implicants, don’t care conditions, Quine-McCluskey method, multi-level minimization.
Week 5 : Design of combinational logic circuits: adders and subtractors, comparator, multiplexer, demultiplexer, encoder, etc.
Week 6 : Representation of Boolean functions: binary decision diagram, Shannon’s decomposition, Reed-Muller canonical form, etc.
Week 7 : Design of latches and flip-flops: SR, D, JK, T. Master-slave and edge-triggered flip-flops. Clocking and timing issues.
Week 8 : Synthesis of synchronous sequential circuits, Mealy and Moore machines, state minimization.
Week 9 : Design of registers, shift registers, ring counters, binary and BCD counters. General counter design methodology.
Week 10: Algorithmic state machine and data/control path design.
Week 11: Asynchronous sequential circuits: analysis and synthesis, minimization, static and dynamic hazards.
Week 12: Testing and fault diagnosis in digital circuits: fault modeling, test generation and fault simulation, fault diagnosis, design for testability and built-in self-test.