Programmable In-Memory Computing Accelerator with 100 SRAM IMC Macros

Explore a cutting-edge presentation from the tinyML Summit 2022 Hardware Session focusing on Programmable In-Memory Computing (IMC) Accelerator technology. Delve into the innovative solution to computation and memory access bottlenecks in conventional hardware accelerators through in-memory computing. Discover the challenges and breakthroughs in integrating and programming system-level IMC accelerators, including the development of a programmable IMC accelerator (PIMCA) with 108 capacitive coupling-based IMC SRAM macros. Learn about the circuit techniques, architecture design, and custom ISA employed in the PIMCA chip, supporting various DNN layer types with improved efficiency. Examine the impressive performance metrics of the 28nm prototype chip, achieving high system-level peak/average energy-efficiency. Gain insights into the future of IMC technology, its limitations, and potential applications in artificial intelligence and deep neural networks.

Introduction
Outline
Background
IMC Macros
Challenges
Limitations
Architecture
PE Mapping
Measurement Comparison
Summary
Questions
Leakage
Accuracy
Future of IMC
Sponsors