Stanford Seminar - The Future of Low Power Circuits and Embedded Intelligence

Explore the future of low power circuits and embedded intelligence in this Stanford seminar. Delve into challenges facing low power circuits, including GALS architecture, Asynchronous NoC, and fine-grain AVFS. Examine adaptive techniques like AVES for mitigating PVT variations and the benefits of FDSOI technology. Investigate 3D stack technologies, their impact on multicore scalability, and applications in imaging and memory-centric architectures. Learn about neuromorphic hardware, spiking neurons, and RRAM. Discover ongoing research in 3D cortical columns and spiking vision systems, offering insights into the cutting-edge developments shaping the future of embedded intelligence and low power circuit design.

Introduction.
Low Power circuits challenges.
GALS : Globally Asynchronous and Locally Synchronous.
Asynchronous NoC (ANOC) and DFS technique • ANOC main features.
Fine-Grain AVFS architecture AVES : Adaptive Voltage and Frequency Scaling : Adaptive architecture to mitigate local but also dynamic PVT variations.
FDSOI brings a new actuator.
FDSOI Back Biasing: an example.
3D stack Technologies @ CEA-Leti.
3D Interconnect and multicore scalabiity • Stacking different technologies.
3D imager: parallel in-focal plane processing.
3D stack process for backside imager.
3D Sequential @ CEA-Leti.
3D stack and sequential: memory-centric architectures.
3D technologies & flexible architectures.
Adaptivity/Flexibility Architecture, New devices and Embedded Intelligence.
Advanced technologies for neuromorphic hardware.
Spiking neurons and RRAM.
Spiking sensors and neuro-DSP.
Work in progress: 3D cortical columns.
Work in progress: 3D spiking vision system.