Stanford Seminar - QED and Symbolic QED- Dramatic Improvements in SoC Validation and Debug
Offered By: Stanford University via YouTube
Course Description
Overview
Syllabus
Introduction.
Staggering IC Complexity.
Post-Silicon Validation Critical.
Post-Silicon Validation Difficult.
Scalability Barriers.
Bigger Obstacles at System Level.
Bug Example.
QED Example: Duplicate & Check Validation program.
QED Example: Duplicate & Check QED Trace.
QED Improves Coverage.
Diversity-Enhanced QED.
QED: Proactive Load & Check.
QED Coverage Considerations.
Error Detection Latency vs. Intrusiveness Improved error detection latency.
Intel® Core™ i7 Hardware.
8-Core QED: Difficult Logic Bugs.
8-Core QED: Power Management Bugs 100%.
Hybrid QED: Logic Bug Results.
Bug Localization.
Symbolic Quick Error Detection.
Traditional Bounded Model Checking.
BOUNDED MODEL CHECKING (BMC).
Traditional BMC vs. Symbolic QED.
BMC Challenge (1): Property.
Universal Property: QED Check.
QED Module.
QED Guarantees Quick Detection.
Partial Instantiation.
Taught by
Stanford Online
Tags
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