Smashing the Implementation Records of AES S-Box

Explore a groundbreaking paper on optimizing AES S-box implementation, presented at CHES 2018. Delve into the innovative approaches proposed by Arash Reyhani-Masoleh, Mostafa M. I. Taha, and Doaa Ashmawy to overcome implementation pitfalls and achieve record-breaking performance. Examine the newly designed AES S-box architecture, logic-minimization algorithms, and improved exponentiation stage. Analyze the impact of output multipliers and target libraries on overall efficiency. Gain valuable insights into state-of-the-art cryptographic engineering techniques and their practical applications in this 21-minute presentation from TheIACR.

Introduction
Implementation Pitfalls
Proposed AES S-box Architecture
Logic-Minimization Algorithms (cont.)
New Exponentiation Stage
New Output Multipliers (cont.)
Comparisons
Effect of Target Library
Concluding Remarks