How to Fuzz an FPGA – My Experience Documenting Gowin FPGAs

Explore the process of fuzzing an FPGA in this 39-minute conference talk from media.ccc.de. Dive into the speaker's experience documenting Gowin FPGAs and learn key concepts for contributing to open-source FPGA tools. Discover the steps involved in synthesis, including writing netlists, creating constraint files, and using Tcl scripts. Gain insights into various fuzzing techniques, such as binary tricks, balanced constant weight, and metaphasers. Examine approaches for routing, data extraction, and speeding up the process. Understand the limitations of clock filters and tile formats in FPGA development. Learn about open-source FPGA projects, APIs, and timing simulators. This talk provides valuable knowledge for those interested in advancing FOSS tools for FPGA development.

Intro
Welcome
Who am I
Outline
Logic tiles
Software
Synthesis
Get the license
Get the FPGA
Get the software
Read the manual
The synthesis tool
What is fuzzing
Step 1 Write a netlist
Step 2 Constraint file
Step 3 Tcl script
Python script
HP run
Binary trick
Balance balanced constant weight
Metaphasers
Routing
Other approaches
GDB example
Datafile example
Automated gdp scripts
Extracting the data
Speedup
Limitations
Clock Filter
Tile Format
Open Source FPGA
Project APIkura
Does Gowin provide a timing simulator