Introduction to HyperBus Memory Devices

Explore the world of HyperBus memory devices in this 36-minute conference talk by Vignesh Raghavendra from Texas Instruments. Dive into the high-performance 8-bit Double Data Rate bus technology connecting SoCs with advanced flash devices. Learn about HyperFlash, a NOR-based, Common Flash Interface (CFI) compliant memory device replacing traditional parallel flashes. Discover the recently introduced HyperBus framework in the Linux kernel's Memory Technology Devices (MTD) subsystem. Gain insights into the HyperBus protocol, CFI specification, and kernel framework. Understand how to develop a new HyperBus Memory Controller Driver and explore improvements made to the CFI framework for supporting HyperFlash. Examine the challenges and unresolved issues in this field. The presentation covers various aspects, including HyperRAM, transaction phases, communication protocols, address space overlays, and comparisons with traditional SPI flash protocols.

Intro
What's in the presentation?
What's HyperBus?
HyperBus Memory Devices
HyperRAM
Phases of a transaction
Communication Protocol
Command Address (CA) Bits
Write Programming Sequence
Address space overlays (ASOs)
Types of HyperBus Memory Controllers (HBMC)
MMIO capable controllers
Kernel support for HyperFlash
Writing a HBMC driver
hyperbus ops
Registering Device
Device Tree representation
Accessing from user space
HyperFlash and SPI
Comparison to traditional SPI flash protocol
XSPI compliant HyperFlash
Extending spl-mem for HyperFlash
Future Enhancements
References