Initializing RISC-V - A Guided Tour for ARM Developers

Explore a comprehensive guided tour of RISC-V architecture tailored for ARM developers in this 50-minute conference talk. Delve into the fundamentals of RISC-V, including timers, code models, and kernel assembly. Examine development platforms, focusing on Barebox implementation on QEMU and BeagleV. Investigate CPU bootup processes, peripherals, and cache coherency concepts. Compare cache coherency mechanisms between ARM and RISC-V architectures. Analyze specific RISC-V implementations like Allwinner D1 and StarFive JH-7100. Learn about privilege modes, trap-and-emulate techniques, and the Supervisor Binary Interface. Gain insights into clock and reset handling for the JH7100 platform, providing a solid foundation for RISC-V development.

Intro
About Me #1
Why do we develop for RISC-V?
RISC-V Overview
RISC-V: Timers
RISC-V: code models
RISC-V: Kernel Assembly
RISC-V: our development platforms
RISC-V: Barebox on qemu
RISC-V Linux Header
RISC-V: Barebox on Beaglev
RISCV: HART(CPU) Bootup
Peripherals
A Primer on Cache Coherency
Cache-Coherent Interconnects
Device mastering the Bus
Linux DMA Mappings
DMA Mappings on ARM
Cache Coherency on RISC-V
Cache In-Coherency on RISC-V
Allwinner Dl (CPU: Alibaba Xuan Tie C906)
StarFive JH-7100 (CPU: SiFive U74)
Privilege Modes
trap-and-emulate
Supervisor Binary Interface
JH7100 Clock/Reset Handling
Got you interested?