HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
Offered By: Scalable Parallel Computing Lab, SPCL @ ETH Zurich via YouTube
Course Description
Overview
Explore a conference talk on HexaMesh, an innovative chiplet arrangement technique for 2.5D integration. Dive into the challenges of scaling to hundreds of chiplets and optimizing inter-chiplet interconnects. Learn about the theoretical and practical advantages of HexaMesh over traditional grid arrangements, including reduced network diameter, improved bisection bandwidth, lower latency, and enhanced throughput. Understand the background of 2.5D integration, key insights, problem statement, and evaluation methods. Gain valuable knowledge on advanced packaging techniques and their impact on large-scale chiplet designs with high-performance interconnects.
Syllabus
Introduction
Background: 2.5D Integration
Key Insights & Problem Statement
Optimizing the Chiplet Arrangement
Evaluation: Theoretical Analysis
Shortcomings of Theoretical Analysis
Evaluation: Simulation Results
Conclusion
Taught by
Scalable Parallel Computing Lab, SPCL @ ETH Zurich
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