ArchTM - Architecture-Aware, High Performance Transaction for Persistent Memory

Explore a conference talk on ArchTM, an architecture-aware, high-performance transaction system for persistent memory. Delve into the innovative design principles aimed at avoiding small writes and encouraging sequential writes to optimize performance on persistent memory devices. Learn about ArchTM's variant of copy-on-write system, its scalable lookup table on DRAM, and the annotation mechanism for ensuring crash consistency. Discover how ArchTM's locality-aware data path in memory allocation increases coalescing writes inside PM devices. Examine the performance comparison between ArchTM and four state-of-the-art transaction systems, showcasing significant improvements in micro-benchmarks and real-world workloads on real persistent memory.

Intro
Persistent Memory (PM) Has Arrived
PM Architecture & Performance Characterization
Transactions on Persistent Memory
Issues of Existing PM Transactions
Issues of Memory Allocation for PM Transactions
Design Goals of ArchTM
Avoid Small Writes on PM
Encourage Coalescable Writes on PM
Recovery Management
Other Optimization Techniques
Evaluation Setup
Evaluation: TPC-C & TATP
Conclusion