Optimizing Systems for Byte-Addressable NVM by Reducing Bit Flipping

Explore optimization techniques for byte-addressable non-volatile memory (BNVM) systems in this USENIX FAST '19 conference talk. Delve into strategies for reducing bit flipping to improve power consumption and extend memory lifetime in phase change memory (PCM) technologies. Examine modifications to common data structures such as linked lists, hash tables, and red-black trees, achieving up to 3.56× reduction in bit flips compared to standard implementations. Learn about the impact of careful data placement in stack frames and memory allocation on bit flip reduction. Discover how these software-based optimizations can be implemented without hardware modifications or significant performance overhead, making them ideal for BNVM-optimized system design.

Introduction
ByteAddressable NVM
Do we do it in software or hardware
Is this something we can do
Data Structures
XOR Linked Lists
Least Significant Bit
RedBlack Tree
Evaluation Criteria
Prior Work
Warmup Results
XOR Linked List Results
Hash Table Results
Red Black Trees Results
Layer 2 Cache Effects
Hash Table Performance
Conclusion
Real Hardware
Questions