Developing the RISC-V Hypervisor Extensions in QEMU

Explore the development of RISC-V Hypervisor Extensions in QEMU through this informative conference talk. Delve into the work done by Alistair Francis and his colleagues at Western Digital to add RISC-V Hypervisor Extension support to QEMU, enabling its use as a development platform for porting Hypervisors to RISC-V. Learn about the functioning of the RISC-V Hypervisor extension and its unique aspects compared to other common architectures. Discover the implementation process in QEMU, challenges encountered with the draft specification, and the current upstream status. Gain insights into pending work related to both QEMU and the RISC-V Hypervisor specification, as well as the porting status of Hypervisor projects. The presentation covers key topics including privilege mode changes, CSR modifications, two-stage MMU, I/O and interrupts handling, and comparisons with AArch64. Conclude with a demonstration of Xvisor running on QEMU, showcasing the practical applications of this development.

Western Digital
Overview
What is a Hypervisor?
RISC-V H-Extension: Spec Status
RISC-V H-Extension. Privilege Mode Changes
RISC-V H-Extension CSR changes
RISC-V H-Extension Two-stage MMU
RISC-V H-Extensions 1/0 & Interrupts
RISC-V Hypervisor Compared to AArch64
Current RISC-V Hypervisors
Current QEMU Implementation
Changes made to QEMU in preparation
Maintaining the Hypervisor State
Two Stage MMU
Handling Register Swapping in QEMU
Future Work
Improvements proposed from QEMU work
Overall Current Status
Xvisor Running on QEMU Demo