Design and Implementation of RISC-V Based LoRa Module for IoT Edge Computing

Explore the design and implementation of a prototype RISC-V based LoRaWAN end node PCB in this 40-minute conference talk. Delve into the integration of FPGA and RISC-V architecture with a LoRa interface to address the growing need for low-power, high-computational IoT end nodes. Learn about the use of the open-source LiteX framework to generate an SoC with necessary cores and peripherals for LoRa transceiver integration. Discover how the design incorporates an ultra-low power FPGA, providing reconfigurable logic, CPU capabilities for data analytics, and standard interfaces for third-party sensors. Examine the custom PCB design in a USB dongle form factor, offering a versatile solution for existing systems requiring enhanced compute power and IoT connectivity. Gain insights into how this innovative approach contributes to minimizing power consumption in data movement and improving real-time response through increased edge data analytics in IoT infrastructures.

Design and Implementation of RISC-V Based LoRa Module - Mark Njoroge, University Of Cape Town