Control of Transmon Qubits Using a Cryogenic CMOS Integrated Circuit

Explore a comprehensive talk on controlling transmon qubits using cryogenic CMOS integrated circuits, presented by Research Scientist Joe Bardin at the APS March Meeting 2020. Delve into the challenges of scaling quantum processors, focusing on the critical classical-to-quantum interface design. Learn about current control and measurement techniques for superconducting quantum processors, including microwave pulse shaping, flux biasing, and dispersive readout. Examine the limitations of room-temperature electronics for large-scale quantum systems and discover the potential of cryogenic quantum control and readout systems using silicon integrated circuit technology. Gain insights into the design and characterization of a prototype cryogenic XY controller for transmon qubits, with detailed measurement results and discussions on future developments. Understand the tradeoffs between coherence time and gate duration, and explore the specifications and key design challenges of cryo-CMOS XY controllers. Analyze waveform generation approaches, block diagrams, and integration into quantum systems for experiments. Compare the performance with state-of-the-art technologies and grasp the importance of scalable control for fault-tolerant quantum computers.

Intro
Outline
Driven Transmon ("Lab Frame")
Tradeoff Between Coherence Time & Gate Duration Gate time avoid
Typical Single Qubit Control/Measurement Hardware
Brute Force Scaling: 54 Qubits
Brute Force Scaling: 138,240 Qubits
Cryo-CMOS XY Controller Specifications Key design challenges: (1) No device models for 3K (2) dissipation
Waveform Generation Approach
Block Diagram
Vector Modulator
Example Room Temperature Measurements
Integration into Quantum System for Experiments
Waveforms at Monitor Port
Feedthrough Cancellation
Rabi Experiment (22ns Pulse)
Coherence Time Measurements
Comparison w/state of the art
Summary • Fault tolerant quantum computers will require scalable control