Place and Route Algorithms for Digital Integrated Circuits

Explore the intricacies of place and route algorithms for digital integrated circuits in this 39-minute conference talk from the 37C3 event. Gain a gentle introduction to the process of transforming a graph-like circuit description (netlist) into a geometrical representation (layout) for silicon chips. Learn about the key steps involved, including IO-planning, floor-planning, power distribution, global placement, clock-tree synthesis, and routing. Discover the input data required, such as netlists, constraints, design rules, and standard-cell libraries. Understand the challenges of meeting timing requirements and the importance of verification in creating valid circuit designs. Focus on widely used algorithms for global placement and basic principles of routing, essential for anyone interested in hardware making and digital circuit design.

37C3 - Place & route on silicon