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Approximate Adder Design for Low-Power Computing - Lecture 12.10

Offered By: NPTEL-NOC IITM via YouTube

Tags

Digital Design Courses VLSI Courses Edge Detection Courses Low-Power Computing Courses

Course Description

Overview

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Explore the concept of approximate adders in this 14-minute lecture from NPTEL-NOC IITM. Delve into two specific approximate adder designs: OLOCA and HOAANED, and learn how they are utilized to create approximate multipliers using array multiplier architecture. Examine the error distribution characteristics and hardware metrics associated with these approximate multipliers. Gain insights into the practical applications of this technology, particularly in edge detection, as referenced in the paper by Yashaswi Mannepalli, Viraj Bharadwaj Korede, and Madhav Rao, presented at the 2021 Great Lakes Symposium on VLSI.

Syllabus

12.10 - Approximate Adder


Taught by

NPTEL-NOC IITM

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