VLSI Design Flow: RTL to GDS

ABOUT THE COURSE:This course covers the entire RTL to GDS VLSI design flow, going through various stages of logic synthesis, verification, physical design, and testing. Besides covering the fundamentals of various design tasks, this course will develop skills in modern chip design with the help of activities and demonstrations on freely available CAD tools. This course will enhance the employability of the students and will make them ready to undertake careers in the semiconductor industry.PREREQUISITES: Basic Course on Digital Circuits (typically taught in the first/second year of UG Program)INDUSTRY SUPPORT: The course develops skills to use design automation tools for chip designing. The course will be valued by companies working on semiconductors, such as Qualcomm, Intel, Texas Instruments, NXP, ST Microelectronics, Micron, IBM, Cadence, Synopsys, Siemens, ARM, AMD, NVidia, Apple, and Google.

Week 1: Basic Concepts of Integrated Circuit I: Structure, FabricationBasic Concepts of Integrated Circuit II: Types, Design Styles, Designing vs. Fabrication,Economics, Figures of MeritOverview of VLSI Design Flow I: Design Flows and AbstractionOverview of VLSI Design Flow II: Pre-RTL Methodology: Hardware/Software Partitioning, SoC Design, Intellectual Property (IP) Assembly, Behavioral SynthesisWeek 2:Overview of VLSI Design Flow III: RTL to GDS Implementation: Logic SynthesisOverview of VLSI Design Flow IV: RTL to GDS Implementation: Physical DesignOverview of VLSI Design Flow V: Verification and TestingOverview of VLSI Design Flow VI: Post-GDS ProcessesWeek 3:Hardware Modeling: Introduction to VerilogSimulation: Testbench, CoverageSimulation: Events, Queues, Mechanism of Simulation in VerilogRTL Synthesis: Verilog Constructs to HardwareWeek 4:Logic Optimization I: Definitions, Two-level logic optimizationLogic Optimization II: Multi-level logic optimizationLogic Optimization III: FSM OptimizationFormal Verification I: IntroductioWeek 5:Formal Verification II: Formal Engines: BDD, SAT SolverFormal Verification III: Combinational Equivalence CheckingFormal Verification IV: Model CheckingTechnology Library: Delay and Power Models of Combinational and Sequential CellsWeek 6:Static Timing Analysis I: Synchronous Behavior, Timing Requirements;Static Timing Analysis II: Timing Graph, Mechanism;Static Timing Analysis III: Delay Calculation, Graph-based Analysis, Path-based Analysis, Accounting for Variations;Constraints: Clock, I/O, Timing ExceptionsWeek 7:Technology MappingTiming-driven OptimizationPower AnalysisPower-driven OptimizationWeek 8:Design for Test I: Basics and Fault ModelsDesign for Test II: Scan Design MethodologyDesign for Test III: ATPGDesign for Test IV: BISTWeek 9:Basic Concepts for Physical Design I: IC Fabrication, FEOL, BEOL;Basic Concepts for Physical Design II: Interconnects and Parasitics;Basic Concepts for Physical Design III: Signal Integrity;Basic Concepts for Physical Design IV: Antenna Effect; Process-induced Variations; LEF filesWeek 10:Chip Planning I: Partitioning;Chip Planning II: Floorplanning: Die Size, I/OCells Chip Planning III: Floorplanning: Macros, Orientation, Pin AssignmentChip Planning IV: Power Planning;Week 11:Placement I: Global Placement, Wirelength EstimatesPlacement II: Legalization, Detailed Placement, Timing-drivenPlacement Placement III: Optimizations, Scan Cell Reordering; Spare Cell PlacementClock Tree Synthesis I: Terminologies, Clock Distribution Networks, Clock Network ArchitecturesWeek 12:Clock Tree Synthesis II: Routing, Useful SkewsRouting: Global and Detailed, OptimizationsPhysical Verification: Extraction, LVS, ERC, DRCECO and Sign-off