Stanford Seminar - A Superscalar Out-of-Order x86 Soft Processor for FPGA

Although FPGAs continue to grow in capacity, FPGA-based soft processors have grown little because of the difficulty of achieving higher performance in exchange for area. Superscalar out-of-order processor microarchitectures have been used successfully for hard processors for many years, but have so far been avoided for FPGAs due to the area increase and the expectation that a loss in clock frequency would more than offset the instructions-per-cycle (IPC) gains.

This talk summarizes my attempt at designing an out-of-order x86 CPU for FPGA. With careful microarchitectural choices and circuit design, I show that it is possible to build a complex microarchitecture on an FPGA, getting about 2.7x performance per clock and 0.8x clock frequency of Altera's Nios II/f single-issue in-order processor. This talk will cover a high-level overview of the microarchitecture and some of the interesting LUT-based circuits used in the processor.

Introduction.
FPGA: Field-Programmable Gate Array.
FPGA Soft Processors.
Faster Soft Processors.
ISA: Why x86.
Soft Processor Design Goals.
How are FPGAs different from CMOS?.
Soft Processor Design Methodology.
Our Processor's Microarchitecture.
Processor Area and Frequency Component.
Per-clock performance (SPECint2000).
Summary 1.
Part 2: Pipeline Details.
Front end: Fetch-decode.
Register Renamer.
Renamer Circuit.
Scheduling: Track dependencies.
Scheduler Size.
Scheduler Circuit.
Scheduler Picker: Bit Scan.
Execution Circuits: Simple ALU.
Execution Circuit: Shifter.
Execution Circuit: Adder.
Memory System Microarchitecture.
Basic Cache Trade-offs.
More Memory System Trade-offs.
L1 Memory System.
What happens to a load: simplified.
Memory System: L1 Circuit.
Summary 2 • Out of order soft processors are useful and feasible.